Download Speedy DDR2 Controller for FPGAs from Official Microsoft Download Center

The Speedy DDR2 controller is intended as an improvement on the Xilinx MIG controller for Virtex 5 FPGAs. Last published: March 18, 2011.

NetStage/DPR: A self-reconfiguring platform for active and passive network security operations - ScienceDirect

Computers, Free Full-Text

A Practical Guide to DDR2 Design with Spartan-3A DSP - ppt download

The CLAS12 Data Acquisition System - ScienceDirect

A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives - ScienceDirect

How to implement high-speed 667 Mbps DDR2 interfaces with FPGAs - EE Times

VHDL by Daniel Lee - Issuu

Computers, Free Full-Text

Xcell Journal issue 77 by Xilinx Xcell Publications - Issuu

Through the Frame-Buffer; or, Thomas and Zack's Adventures in FPGA-Land, by Zachary Robinson

Spartan 6 FPGA Family

FPGA Board (Nexys A7-100T) User Guide.pdf

Download - Farnell